Immediately Require Senior E/E & Semiconductor Engineer - Validation and Emulation Engineer in Santa Clara, CA
Job title: Senior E/E & Semiconductor Engineer - Validation and Emulation Engineer
Company: Capgemini
Job description: Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
- Flexible work
- Healthcare including dental, vision, mental health, and well-being programs
- Financial well-being programs such as 401(k) and Employee Share Ownership Plan
- Paid time off and paid holidays
- Paid parental leave
- Family building benefits like adoption assistance, surrogacy, and cryopreservation
- Social well-being benefits like subsidized back-up child/elder care and tutoring
- Mentoring, coaching and learning programs
- Employee Resource Groups
- Disaster Relief
- Expertise in using either ZeBU server 4/Veloce Virtual Lab, veloce power or Palladium App emulation tools.
- Able to build hybrid model to integrate virtual models with emulated models and bring up of SOC Emulation test environment.
- Experience working on at least 2 ASIC/FPGA Prototyping Projects
- Able to work independently on OVM/UVM test-bench and proficiency in re-run the UVM based simulation tests in emulation with minimal changes.
- Tweak existing emulation environment to achieve time reduction.
- Implement projects in Storage/Networking applications/datacenter SOC's.
- Knowledge of running stress/performance tests and good to have experience running/debugging SCAN/MBIST patterns.
- Exposure to FPGA programming and FPGA tools will be useful.
- Experience level 7 to 15 years.
- Experience with SV+UVM/OVM/VMM or Specman/eRM/UVMe
- Contribute to verification environment development.
- Experience with SOC with C/ASM based tests, Graphics or CPU is an added advantage.
- Experience in Tcl/Tk, PERL, Python is a plus.
- Experience of formal verification using Jasper is nice to have.